Auryn simulator

Simulator for spiking neural networks with synaptic plasticity

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manual:xeonphi [2014/07/10 08:55] – [Running Auryn simulations on the Intel® Xeon Phi™ Product Family (MIC architecture)] zenkemanual:xeonphi [2014/07/22 11:25] – Adds link to Intel homepage zenke
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 ====== Running Auryn simulations on the Intel® Xeon Phi™ Product Family (MIC architecture) ====== ====== Running Auryn simulations on the Intel® Xeon Phi™ Product Family (MIC architecture) ======
  
-The following section is experimental. To compile Auryn in native mode for the Intel Xeon Phi cards the following steps worked. Requirements: First, use the newest Auryn development version, which does not compile against GSL any more. This saves you some extra troubel in compiling GSL. Second, you need the Intel Composer suite. Third, you need the boost libraries (see [[required libraries]]) compiled for the intel MIC architecture ideally using the Intel MPI implementation which is native to Xeon and the Xeon Phis. +The following section is experimental. To compile Auryn in native mode for the [[http://www.intel.com/content/www/us/en/processors/xeon/xeon-phi-detail.html|Intel Xeon Phi]] cards the following steps worked. Requirements: First, use the newest Auryn development version, which does not compile against GSL any more. This saves you some extra troubel in compiling GSL. Second, you need the Intel Composer suite. Third, you need the boost libraries (see [[required libraries]]) compiled for the intel MIC architecture ideally using the Intel MPI implementation which is native to Xeon and the Xeon Phis. 
  
 This has been tested for the development version available on [[https://github.com/fzenke/auryn|GitHub]] as commit ''5b02d058844ea9b6344cc4e94491c10cf5ea0522''. This has been tested for the development version available on [[https://github.com/fzenke/auryn|GitHub]] as commit ''5b02d058844ea9b6344cc4e94491c10cf5ea0522''.
manual/xeonphi.txt · Last modified: 2014/12/15 12:54 by zenke